EMI (Electromagnetic Interference: unwanted electromagnetic radiations) is generated from printed circuit boards (hereinafter also referred to as “PCB”) mounted in electronic devices. A main cause of the EMI generation may possibly be a high-frequency current on a PCB, particularly, a high-frequency current from a power supply pin of a semiconductor integrated circuit (Large Scale Integrated Circuit, hereinafter also referred to as “LSI”). Accordingly, as countermeasures to the EMI of electronic devices, a high-frequency current flowing through the power supply circuit network layer of a PCB needs to be estimated during a designing stage of the PCB. To this end, a suitable LSI power pin model for use in an EMI simulation is required.
Increasingly larger roles, including an analysis of a current leaking into a signal system, an analysis of the stability of a semiconductor upon signal switching of a power supply voltage, and the like, but not limited to the EMI simulation, have been required for the LSI power pin model.
As shown in FIG. 1, a conventional LSI power pin model is typically of a simple configuration which comprises, between power supply pins of an LSI, active section 91 which is a power supply, and internal capacitance section 92 which is in parallel with active section 91. This power model is adapted to be used by connecting, as part of wires of a distributed power supply circuit network wire models of resistive elements to the upper and lower terminals. This power pin model has a sufficient accuracy because the current flowing from the power supply pin of the LSI to the outside fluctuates due to an external load.
A method of designing such a power pin model is proposed in Patent Literature 1 entitled “Method, Apparatus, and Program for Creating a Semiconductor Integrated Circuit Power pin model of EMI simulation.” This literature describes a power pin model in which an active section of a power supply is described as a variable resistor plus a load capacitance, and is configured to control the value of a power supply current of an LSI by the operation of the variable resistor. Patent Literature 2 entitled “Power pin model of a Semiconductor Integrated Circuit for EMI Simulation, and Method of Creating Same” describes a model in which, for an active section of a power supply, a model is used that is described using transistors, and for internal capacitances, a combination of models which depend on the operating state of transistors within an LSI, and models of capacitances that take into account the junction capacitance generated from the structure of the LSI, is used.
However, with the recent greater increase of LSIs in scale and speed, it has been pointed out that the aforementioned simple model is no longer enough. When an LSI is large in size, an active section and an internal capacitance section of the LSI are distributed within the LSI. According to the description of a conventional power supply, this is of a structure where only one power pin model 93 is present centrally in the LSI, as shown in FIG. 2. In this case, although a plurality of packages and wires of PCB exist in the LSI, the differences between currents which flow through the packages cannot be correctly estimated because no consideration is given to positional information on the active section and internal capacitances of the LSI. In addition, a power supply circuit network wire has been represented by simple resistive element 94 alone, as illustrated in the figure; but since a power supply circuit network is increasingly complicated, there arises the need to perform accurate modeling. In the prior art, since analysis frequency in a model is low, even a simple model shown in FIG. 1 exhibits a sufficient accuracy. However, since the frequency of concern is caused to rise owing to the speed-up of LSIs, the conventional simple model is no longer sufficient.
As countermeasures to such a situation, an example of a new semiconductor device model for analyzing noise on power supply and a method of creating the same is described in Patent Literature 3 entitled “Semiconductor Device Model, and Method and Apparatus for Creating the same.”
This patent literature concerns a method of creating a semiconductor device model for use in analyzing behaviors of noise on power supply in a semiconductor device. In this method, in order to accurately analyze noise on power supply, models (sub-models) of a power supply circuit network wire, internal capacitances, an internally consumed current, and input/output cells for a semiconductor device to be subjected to noise on power supply analysis are created and these models (sub-models) of the power supply circuit network wire, internal capacitances, internally consumed current, and input/output cells are coupled to thereby create a semiconductor device model for noise on power supply analysis.
In regard to the shape of the model, a power supply circuit network layer of the LSI is divided into a specified number of areas in a reticular pattern. The resistance and inductance of the power supply circuit network wire that are present in each of the divided areas (power supply circuit network lattices) are assigned to a cross-shaped circuit model to create a sub-model of the power supply circuit network wire. Further, models of noise sources and models of internal capacitances are coupled to the center of each power supply circuit network wire sub-model, thus representing actual current operations.
Thus, the capacitance distribution within an LSI can be defined even in a large-scale LSI, thus making it possible to create a more precise model.
However, this method fails to describe how to determine a specific division number. It is thought that an optimal division number can be found by repeating the analysis while changing the division number. However, since there are no specific guidelines for the division number, an excessively large division number would require more analysis time than is necessary, while an excessively small division number would result in a failure to achieve a sufficient degree of analysis accuracy. Furthermore, the repetition of increasing and decreasing the division number to find an optimal division number will require man-hours therefor.                Patent Literature 1: JP-2002-304434A;        Patent Literature 2: JP-2001-222573A;        Patent Literature 3: JP-2004-234618A.        